Manual Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics

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  1. Recommended for you
  2. My Research Paper
  3. Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics
  4. Design Systems for VLSI Circuits
  5. Product details

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While another embodiment of the invention enables signals to be shielded by opposite power and ground grids on left, right, top and bottom. More specifically, an embodiment of the present invention is drawn to an integrated circuit device comprising: a a plurality of signal lines disposed within a substrate; b a power grid disposed on the substrate and comprising: a plurality of power lines having a first thickness; and a plurality of ground lines having the first thickness, the power grid for supplying power and ground to circuitry of the substrate; and c a shield mesh disposed on the substrate and comprising: a plurality of power lines having a second thickness; and a plurality of ground lines having the second thickness, wherein respective signal lines of the plurality of signal lines are disposed between a respective power line of the shield mesh and a respective ground line of the shield mesh, the shield mesh for reducing the effects of electronic cross-talk between nearby signal lines of the plurality of signal lines.

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Embodiments include the above and wherein the power and ground lines of the shield mesh are alternatively disposed and parallel to each other within a single metal layer of the substrate. Other embodiments include an integrated circuit as described above generally and wherein the power and ground lines of the shield mesh are alternatively disposed in a first direction parallel to each other within a first metal layer of the substrate and wherein the power and ground lines of the shield mesh are also alternatively disposed in a second direction parallel to each other within a second metal layer of the substrate, the second metal layer being underneath the first metal layer and wherein the first and second directions are 90 degrees apart.

The present invention is illustrated by way of example and not by way of limitations in the figures accompanying drawings in which like reference numerals refers to similar elements and in which:. Reference will now be made in detail to the embodiments of the invention, a shield power and ground mesh to remove both capacitive and inductive signal coupling effects of routing in ASIC chips, examples of which are illustrated in the accompanying drawings.

While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention.


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However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to obscure aspects of the present invention unnecessarily. The present invention describes a circuit device that comprises a plurality of signal lines of given thickness disposed within a substrate that will in addition to providing power to the circuitry of said substrate circuit, will also perform as a shielding mesh that is utilized to reduce the effects of cross-talk between nearby signal lines of said plurality of signal lines within said circuit.

As shown in depiction of FIG. As discussed earlier, for sub-micron technologies, the lengths of these signal and shield lines can become relatively long up to uM with respect to line thickness for example: as short as 0. According to one embodiment of the present invention, , FIG. On another layer, e.

In accordance with one embodiment of the present invention it is appreciated that the shield mesh is included on an IC in addition to a power grid used to supply power and ground to the circuitry. According to another embodiment, for example in a 0. According to another embodiment, , of the present invention, FIG. Therefore, FIG.

According to an embodiment of shield mesh of the present invention, FIG. According to another embodiment, FIG.

Each via provides layer connections and also reduces the segment size of the shielding mesh and thereby reduces the effective R-C resistance according to one embodiment of the present invention. It is important to note that on layer N, A, if the signal lines , and are on odd grid tracks, then the VDD and VSS lines will be on even grid tracks, and vice-versa. Multi-layer routing assignment to signals and shields: for the vertical space, the track assignment should be done so that there would not be signal tracks directly on top of one another to avoid top bottom coupling.

Interconnect Modeling (Part 2)

Thereby, further reducing the segment lengths and increasing the effective isolation between signal lines to reduce noise coupling. As seen FIG. Therefore, the shield mesh of FIG. Another embodiment of the present invention connects adjacent layers by means of vias as shown in elements A through N. According to another embodiment of the present invention, this multi-layer shielding mesh reduces each component length and thereby according to one embodiment of the present invention, further reduces the coupling effects.

Likewise, according to another embodiment of the present invention, signal lines A, B and C can also be traced to have shielding on both adjacent side-by-side layers as well as vertical top-to-bottom layers. This multi-layer shielding mesh reduces each component length and thereby according to one embodiment of the present invention, further reduces the coupling effects in a gridless routing technique. As shown in vias and , the distance between segment size is not bound by grid width.

This gridless example can again be seen in vias and According to another embodiment of the present invention, vias of varying sizes can be utilized in as close proximity as possible without dependency of grid size. Utilizing the close proximity of the vias, relative segment lengths of each signal, VDD or VSS shielding mesh is reduced. According to another embodiment of the present invention, the shielding mesh is utilized to provide a path for connecting an integrated circuit device to the main power grid. As shown in FIG.

According to embodiment, , FIG. The shielding mesh is utilized to reduce the capacitive and inductive effects of cross-talk while the power grid is provided to deliver power and ground to IC circuits. The lines of the power grid are much larger than the VSS and VDD lines of the shielding mesh, which are sized to be the size of the signal lines. According to this embodiment, the size difference between the shielding mesh lines and the true power grid lines may vary by factor of 2 to factor of However, due to their relative small segment lengths, the shielding mesh in function, reduces the effective RC component of the lines being connected to.

This in turn reduces the noise and coupling effect and therefore, the shielding mesh can be deployed on any substrate area where routing resources are used. As described in FIG. As shown in this embodiment of the present invention, initial code is generally written using HDL, step , for example after which logic synthesis, step , is performed.

My Research Paper

Placement of a power grid is next performed as shown in block For example where substrate grid is utilized, shielding mesh as outlined in one embodiment of the present invention can be introduced as shown at point After this point, the router, , will route the designed circuit and handle the shielding mesh within its parameters. At this point, the design is put on tape However, it is important to note that it is not necessary to introduce the shielding mesh on a substrate grid. As described earlier, another embodiment of the present invention allows for said shielding mesh to be introduced in a gridless design on a given substrate.

For gridless routing, router can introduce the shielding mesh into the said substrate. This fully connected power and ground shielding mesh can be used when it is important to remove capacitive and inductive coupling. The main sources for this mesh would be from the main power grid trunks or independent power and ground trunks dedicated for shielding where they are relatively noiseless. The shielding mesh can also be used in standard cell or gate array routing area, routing channels or routing channels on top of hard macros, data bus routing, control bus routing, address bus routing, analog signal routing, clocks and clock bus routing, or any other signal lines.

With the addition of this fully connected power and ground shielding mesh, the automated VDSM chip routing can be much more worry-free, and almost unpredictable coupling errors can be virtually eradicated by the present invention. Effective date : Year of fee payment : 4. Year of fee payment : 8. Year of fee payment : A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling.

Relatively long signal lines are routed in between fully connected power and ground shield mesh which may be generated by a router during the signal routing phase or during power mesh routing phase.

Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics

Leaving only the odd tracks or the even tracks for signal routing, power mesh VDD and ground mesh VSS are routed and fully interconnected leaving shorter segments and thereby reducing the RC effect of the circuit device. Another embodiment presents a technique where the signals are shielded using the power and ground mesh for a gridless routing. Another embodiment presents a multi-layer grid routing technique where signals are routed on even grid and the power and ground lines are routed on odd grid. Another embodiment enables signals to be shielded by opposite power and ground grids on left, right, top and bottom.

Field of the Invention The field of the present invention pertains to circuitry to solve the problems caused by capacitive and inductive coupling in signals in an integrated circuit device. Related Art With their growth in commercial markets and consumer demands for smaller Integrated Circuits ICs—which are used in numerous applications such as cellular phones, wristwatch cameras, and hand-held organizers just to name a few increase, IC size requirement trends continue towards a small form factor and lowered power consumption.

The present invention describes a circuit device that comprises a plurality of signal lines of given thickness disposed within a substrate that will in addition to providing power to the circuitry of said substrate circuit, will also perform as a shielding mesh that is utilized to reduce the effects of cross-talk between nearby signal lines of said plurality of signal lines within said circuit As shown in depiction of FIG. A method of designing an integrated circuit IC , said method comprising: creating a representation of a shielding mesh in at least one layer of said IC, said shielding mesh having a first plurality of lines which are designed to provide a first reference voltage and having a second plurality of lines which are designed to provide a second reference voltage;.

A method as in claim 1 , wherein the method is performed at least in part by an EDA tool. A method as in claim 2 , wherein said method uses initial code written in an HDL.

Design Systems for VLSI Circuits

A method of designing an integrated circuit IC , the method comprising: generating a representation of at least one signal line;. The method of claim 4 , wherein the first conductor and the second conductor are not parallel. The method of claim 4 , wherein the first conductor and the second conductor are in close proximity.

The method of claim 6 , wherein the method is performed at least in part by an EDA tool. The method of claim 4 , wherein thickness of said first conductor is substantially the same as thickness of said at least one signal line.

Product details

The method of claim 8 , wherein an angle between a first direction along said first conductor and a second direction along said second conductor is substantially close to 90 degrees. The method of claim 4 , wherein said first conductor is substantially close to a signal line from said at least one signal line, said signal line being substantially parallel to said first conductor. Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device.

USB2 en. In this way, the fabric concept eliminates cross-talk up-front, and by design. We propose two separate design flows, each of which uses the fabric concept to implement logic. We call these cells fabric cells, and they have the same logic functionality as existing standard cells with which they are compared. Here at Walmart. Your email address will never be sold or distributed to a third party for any reason. Due to the high volume of feedback, we are unable to respond to individual comments. Sorry, but we can't respond to individual comments.

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Product Highlights This book was motivated by the problems being faced with shrinking IC process feature sizes. Cross-talk is one of the major problems since i. About This Item We aim to show you accurate product information. Manufacturers, suppliers and others provide what you see here, and we have not verified it.